Variability and Voltage Supply Scaling in Limited Switch Dynamic Logic

Abstract—The limited switch dynamic logic (LSDL) family is a hybrid of dynamic and static logic which purports to provide the best of both worlds, namely high performance at low power consumption. In this study, the power-performance tradeoff in LSDL is studied, with an emphasis on operation at low supply voltages. LDSL will be compared to static and domino logic in using 45 nm CMOS technology simulations for several simple circuit implementations, including an inverter, three-input NAND and NOR gates, a two-input multiplexer, and a full adder. Area will be considered only in the context of its contribution to wire loading. The relative robustness of the three logic styles to process variation and noise will also be investigated. Finally, feasibility of incorporating LSDL into automated layout and design tools will discussed