Abstract — Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is proposed to compute the longest path length distribution for directed graphs with cycles. Our SBF algorithm efficiently computes the statistical longest path length distribution if there exist no positive cycles or detects one if the circuit is likely to have a positive cycle. An important application of SBF is Statistical Retimingbased Timing Analysis (SRTA), where SBF is used to check for the feasibility of a given target clock period distribution for retiming. Our gate and wire delay distribution model considers several high-impact intra-die process paramet...
Variability in process parameters is making accurate timing anal-ysis of nano-scale integrated circu...
The 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26-29 May 201...
DoctorAggressive technology scaling in feature size has propelled designers to integrate millions of...
Abstract—Process variations in digital circuits make sequential circuit timing validation an extreme...
Abstract—In this paper we present the Statistical Retiming-based Timing Analysis (SRTA) algorithm. T...
The effect of process variation is getting worse with every technology generation. With variability ...
The effect of process variation is getting worse with every technology generation. With variability ...
Abstract—As process variations become a significant problem in deep sub-micron technology, a shift f...
[[abstract]]We propose a false-path-aware statistical timing analysis framework. In our framework, c...
In this paper, we highlight a fast, effective and practical statistical approach that deals with int...
Abstract—To increase the accuracy of static timing analysis, the traditional nonlinear delay models ...
We propose a false-path-aware statistical timing analysis frame-work. In our framework, cell as well...
Abstract—Recent advances in statistical timing analysis (SSTA) achieve great success in computing ar...
Abstract—To improve the accuracy of static timing analysis, the traditional nonlinear delay models a...
The move to deep submicron processes has brought about new problems that designers must contend with...
Variability in process parameters is making accurate timing anal-ysis of nano-scale integrated circu...
The 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26-29 May 201...
DoctorAggressive technology scaling in feature size has propelled designers to integrate millions of...
Abstract—Process variations in digital circuits make sequential circuit timing validation an extreme...
Abstract—In this paper we present the Statistical Retiming-based Timing Analysis (SRTA) algorithm. T...
The effect of process variation is getting worse with every technology generation. With variability ...
The effect of process variation is getting worse with every technology generation. With variability ...
Abstract—As process variations become a significant problem in deep sub-micron technology, a shift f...
[[abstract]]We propose a false-path-aware statistical timing analysis framework. In our framework, c...
In this paper, we highlight a fast, effective and practical statistical approach that deals with int...
Abstract—To increase the accuracy of static timing analysis, the traditional nonlinear delay models ...
We propose a false-path-aware statistical timing analysis frame-work. In our framework, cell as well...
Abstract—Recent advances in statistical timing analysis (SSTA) achieve great success in computing ar...
Abstract—To improve the accuracy of static timing analysis, the traditional nonlinear delay models a...
The move to deep submicron processes has brought about new problems that designers must contend with...
Variability in process parameters is making accurate timing anal-ysis of nano-scale integrated circu...
The 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26-29 May 201...
DoctorAggressive technology scaling in feature size has propelled designers to integrate millions of...