Single region vs. multiple regions: A comparison of different compiler-directed dynamic voltage scheduling approaches

Abstract. This paper discusses the design and implementation of a profile-based power-aware compiler using dynamic voltage scaling. The compiler identifies program regions where the CPU can be slowed down without resulting in a significant overall performance loss. Two strategies have been implemented inSUIF2.The single-region strategy slows down a single region for energy savings, while the multiple-region strategy slows down as many regions as needed. A comparison of both strategies based on six SPECfp95 benchmarks shows that in five out of six cases, the energy-delay product and energy/performance tradeoffs were comparable. In the remaining case, the multiple regions approach was significantly better. Both strategies achieved energy savings of up to 48 % for the five programs at the slowdown between 1 % and 16%, and energy savings of 74 % for the multiple regions vs. 50 % for the single region strategy for the remaining program at the slowdown up to 21%.