The High Performance Local Radio Area Network

This paper presents an implementation of a channel equalizer for a wireless OFDM according to the IEEE 802.11a and Hiperlan/2 standard. In order to implement the equalizer, algorithms of low computational complexity have been analyzed. A rapid prototype design flow is presented and applied to the prototyping of these equalizer algorithms in real time on a FPGA platform. A new point of view in the prototyping design flow and the verification process is achieved through the last generation system level design environments for DSPs into FPGAs. These environments, called visual data flows, are ideally suited for modeling DSP systems, since they allow a high level of functional abstraction with different data types and operators. The implemented channel equalizer reaches a high degree of hardware simplicity and efficiency, covering the standard specifications