Abstract This paper describes a new data structure, difference decision diagrams (DDDs), for representing a Boolean logic over inequalities of the form ¡£¢¥¤§¦©¨ where the variables are integer or real-valued. We give algorithms for manipulating DDDs and for determining validity, satisfiability, and equivalence. DDDs enable an efficient verification of timed systems modeled as, for example, timed automata or timed Petri nets, since both the states and their associated timing information are represented symbolically, similar to how BDDs represent Boolean predicates. We demonstrate the efficiency of DDDs by analyzing a timed system and compare the results with the tools KRONOS and UPPAAL.
textabstractThe logic of equality and uninterpreted functions (EUF) has been proposed for processor ...
... graphs. They form a canonical representation, making testing of functional properties such as sa...
In this report, we suggest interval diagram techniques for formal verification of timed automata. I...
Abstract This paper describes a new data structure, difference decision diagrams (DDDs), for represe...
AbstractWe describe a novel methodology for analyzing timed systems symbolically. Given a formula re...
In this paper we analyze the efficiency of binary decision diagrams (BDDs) and clock difference diag...
AbstractThis paper presents a new data structure called boolean expression diagrams (BEDs) for repre...
In this paper, we present Clock Difference Diagrams (CDD), a new BDD-like data-structure for effecti...
International audienceIn this paper we suggest numerical decision diagrams, a BDD-based data structu...
Ordered Binary Decision Diagrams (OBDDs) represent Boolean functions as directed acyclic graphs. The...
Binary Decision Diagrams (BDDs) provide a compact representation for Boolean functions. This researc...
Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as form...
Symbolic verification has received much attention from both academia and industry in the past two de...
We present a new approach to unbounded, fully symbolic model checking of timed automata that is base...
The logic of equality and uninterpreted functions (EUF) has been proposed for processor verification...
textabstractThe logic of equality and uninterpreted functions (EUF) has been proposed for processor ...
... graphs. They form a canonical representation, making testing of functional properties such as sa...
In this report, we suggest interval diagram techniques for formal verification of timed automata. I...
Abstract This paper describes a new data structure, difference decision diagrams (DDDs), for represe...
AbstractWe describe a novel methodology for analyzing timed systems symbolically. Given a formula re...
In this paper we analyze the efficiency of binary decision diagrams (BDDs) and clock difference diag...
AbstractThis paper presents a new data structure called boolean expression diagrams (BEDs) for repre...
In this paper, we present Clock Difference Diagrams (CDD), a new BDD-like data-structure for effecti...
International audienceIn this paper we suggest numerical decision diagrams, a BDD-based data structu...
Ordered Binary Decision Diagrams (OBDDs) represent Boolean functions as directed acyclic graphs. The...
Binary Decision Diagrams (BDDs) provide a compact representation for Boolean functions. This researc...
Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as form...
Symbolic verification has received much attention from both academia and industry in the past two de...
We present a new approach to unbounded, fully symbolic model checking of timed automata that is base...
The logic of equality and uninterpreted functions (EUF) has been proposed for processor verification...
textabstractThe logic of equality and uninterpreted functions (EUF) has been proposed for processor ...
... graphs. They form a canonical representation, making testing of functional properties such as sa...
In this report, we suggest interval diagram techniques for formal verification of timed automata. I...