In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for “local ” whitespace is further emphasized by temperature and power-density limits as well as the increasing use of buffered interconnect. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic re-synthesis targeting local congestion in a given placement or particular critical paths may be irrelevant for another placement pro-duced by the same or ...
This dissertation examines the extension of constructive library-aware logic synthesis to the physic...
This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. ...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...
Placement plays a fundamental and critical role in the physical design of integrated circuits. The t...
Increased transistor density in modern commercial ICs typically originates in new manufacturing and ...
The use of white space in fixed-die standard-cell placement is an ef-fective way to improve routabil...
textThe nature of multiple objectives and incremental design process for modern VLSI design closure...
In a VLSI physical synthesis flow, placement directly defines the interconnection, which affects ma...
We present new concepts to integrate logic synthesis and physical design. Our methodology uses gener...
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die contex...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
Traditionally, interconnect effects are taken into account during logic synthesis via wireload model...
Abstract—In order to achieve timing closure on increasingly complex IC designs, buffer insertion nee...
Abstract—In order to achieve timing closure on increasingly complex IC designs, buffer insertion nee...
This dissertation examines the extension of constructive library-aware logic synthesis to the physic...
This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. ...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...
Placement plays a fundamental and critical role in the physical design of integrated circuits. The t...
Increased transistor density in modern commercial ICs typically originates in new manufacturing and ...
The use of white space in fixed-die standard-cell placement is an ef-fective way to improve routabil...
textThe nature of multiple objectives and incremental design process for modern VLSI design closure...
In a VLSI physical synthesis flow, placement directly defines the interconnection, which affects ma...
We present new concepts to integrate logic synthesis and physical design. Our methodology uses gener...
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die contex...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
Traditionally, interconnect effects are taken into account during logic synthesis via wireload model...
Abstract—In order to achieve timing closure on increasingly complex IC designs, buffer insertion nee...
Abstract—In order to achieve timing closure on increasingly complex IC designs, buffer insertion nee...
This dissertation examines the extension of constructive library-aware logic synthesis to the physic...
This research is situated in the design of integrated circuits (ICs). ICs are virtually everywhere. ...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...