This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed method consists of three steps: (1) functional-cluster formation, (2) slack computation, and (3) set-coveringbased partitioning with functional replication. The proposed method performs multi-FPGA partitioning by taking into account path delays and design structural information. We introduce a functional replication technique which performs circuit replications at the functionalcluster level instead of the cell level for delay and interconnect minimization. Experimental results on a number of benchmarks and industrial designs demonstrate that the proposed method achieves high-performance and high-density multi-FPGA partitions.
[[abstract]]The authors propose an efficient and effective algorithm for system partitioning under t...
Abstract—A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and i...
This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed ...
[[abstract]]This paper presents a new performance-driven partitioning method for multi-FPGA designs....
[[abstract]]In this paper, we present a new integrated synthesis and partitioning method for multipl...
[[abstract]]In this paper, we present a new integrated synthesis and partitioning method for multipl...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
Our approach to the problem of partitioning the design (represented as a hypergraph) into Multi-FPGA...
Abstract—Most high performance computing systems are large-scale computing systems, and consist tens...
In this paper, we present a new synthesis and parti-tioning approach for multiple-FPGA implementatio...
This paper considers the problem of partitioning a circuit into a collection of subcircuits, such th...
In this paper, we introduce a new recursive partitioning paradigm PROP which combines partitioning, ...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
It takes a long time to generate a configuration for an FPGA starting from a description of a digita...
One of the critical issues for multi-FPGA systems is developing software tools for automatically map...
[[abstract]]The authors propose an efficient and effective algorithm for system partitioning under t...
Abstract—A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and i...
This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed ...
[[abstract]]This paper presents a new performance-driven partitioning method for multi-FPGA designs....
[[abstract]]In this paper, we present a new integrated synthesis and partitioning method for multipl...
[[abstract]]In this paper, we present a new integrated synthesis and partitioning method for multipl...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
Our approach to the problem of partitioning the design (represented as a hypergraph) into Multi-FPGA...
Abstract—Most high performance computing systems are large-scale computing systems, and consist tens...
In this paper, we present a new synthesis and parti-tioning approach for multiple-FPGA implementatio...
This paper considers the problem of partitioning a circuit into a collection of subcircuits, such th...
In this paper, we introduce a new recursive partitioning paradigm PROP which combines partitioning, ...
[[abstract]]In this paper, we propose the idea of temporal logic replication in dynamically reconfig...
It takes a long time to generate a configuration for an FPGA starting from a description of a digita...
One of the critical issues for multi-FPGA systems is developing software tools for automatically map...
[[abstract]]The authors propose an efficient and effective algorithm for system partitioning under t...
Abstract—A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and i...
This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed ...