A Model for Transient Faults in Logic Circuits

Abstract: Transient (soft) faults due to particle strikes and other environmental and manufacturing effects are a frequent cause of failure in ICs. We propose a general, technology-independent model called single transient fault (STF) model to represent transient faults and errors in logic circuits. It is defined in terms of a temporary stuck-at fault and its associated circuit state. STFs can be used to estimate the transient error probability p err of a circuit’s nodes, as well as various measures of reliability and error tolerance. We demonstrate the use of STFs with combinational and sequential logic circuits, including several types of adders. Some other applications of STFs are also briefly considered