TRUNCATED ON-LINE ARITHMETIC WITH APPLICATIONS TO COMMUNICATION SYSTEMS

Truncation in digit-precision is a very important and common operation in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use of on-line arithmetic to provide truncated computations with communication systems as one of the applications. In contrast to truncation in conventional arithmetic, on-line arithmetic can truncate dynamically and produce both area and time benefits due to the digitserial nature of computations. This is of great advantage in communication systems where the precision requirements can change dynamically with the environment. While truncation in conventional arithmetic can have significant truncation errors, especially when the output precision is less than the input precision, the redundancy and most significant digit first nature of on-line arithmetic restricts the truncation error to only the least significant digit of the truncated result. As an application that uses significant truncation in precision, a code matched filter detector for wireless systems is designed using truncated on-line arithmetic. The detector can provide both hard decisions and soft(er) decisions dynamically as well as interface with other conventional arithmetic circuits or act as a DSP co-processor. Thus, optimized communication receivers with co-existing conventional arithmetic for saturation and on-line arithmetic for truncation can now be built. The truncated on-line arithmetic detector was also verified with a VLSI implementation in an AMI 0.5 µ MOSIS tiny chip process