Abstract: The width of an interconnect line affects the total power consumed by a circuit. A trade off exists between the dynamic power and the short-circuit power dissipated in inductive interconnect. The optimum line width that minimizes the total transient power dissipation is determined in this paper. A closed form solution for the optimum width with an error less than 5 % is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 78 % is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined
Abstract—This paper presents a detailed empirical study and an-alytical derivation of voltage wavefo...
High di/dt ratios, large current pulses over short times, are an inevitable part of today’s fast ele...
To obtain higher performance with maximum devices and smaller chip size semiconductor devices are co...
A large part of today's multi-core chips is interconnect. Increasing communication complexity has ma...
In this paper, we study the modeling and layout optimization for on-chip interconnect structures to ...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
As technology scales, interconnect planning has been widely regarded as one of the most critical fac...
The exponential shrinking of the feature size, together with the consistent growth of the chip size ...
As scaling of technology continues to the Deep Sub-Micron (DSM) regime, some papers claimed that on-...
An optimal width design for an electromigration-free interconnect in CMOS technology has been develo...
A large part of today's multi-core chips is interconnect. Increasing communication complexity has ma...
Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a signi...
Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a signi...
This book provides practical solutions for delay and power reduction for on-chip interconnects and b...
Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of ...
Abstract—This paper presents a detailed empirical study and an-alytical derivation of voltage wavefo...
High di/dt ratios, large current pulses over short times, are an inevitable part of today’s fast ele...
To obtain higher performance with maximum devices and smaller chip size semiconductor devices are co...
A large part of today's multi-core chips is interconnect. Increasing communication complexity has ma...
In this paper, we study the modeling and layout optimization for on-chip interconnect structures to ...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
As technology scales, interconnect planning has been widely regarded as one of the most critical fac...
The exponential shrinking of the feature size, together with the consistent growth of the chip size ...
As scaling of technology continues to the Deep Sub-Micron (DSM) regime, some papers claimed that on-...
An optimal width design for an electromigration-free interconnect in CMOS technology has been develo...
A large part of today's multi-core chips is interconnect. Increasing communication complexity has ma...
Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a signi...
Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a signi...
This book provides practical solutions for delay and power reduction for on-chip interconnects and b...
Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of ...
Abstract—This paper presents a detailed empirical study and an-alytical derivation of voltage wavefo...
High di/dt ratios, large current pulses over short times, are an inevitable part of today’s fast ele...
To obtain higher performance with maximum devices and smaller chip size semiconductor devices are co...