Add to ORKGClosed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently have large blocks that make the ideal buffer insertion solution unrealizable. The theory of [12] is extended to show how one can model the blocks into a simple delay estimation technique that applies both to two-pin and to multi-pin nets. Even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer insertion solution. Potential applications include wire planning, timing analysis during floorplanning or global routing. Our experiments show that our a...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
To implement high-performance global interconnect without impact-ing the performance of existing blo...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
Closed formed expressions for buffered interconnect delay approximation have been around for some ti...
As devices and lines shrink into the deep submicron range, the propagation delay of signals can be e...
Abstract During the routing of global interconnects, macro blocks form useful routing regions which ...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
We describe a new algorithm for floorplan evalua-tion using timing-driven buffered routing according...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron des...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according ...
To implement high-performance global interconnect without impacting the performance of existing bloc...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
To implement high-performance global interconnect without impact-ing the performance of existing blo...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...
Closed formed expressions for buffered interconnect delay approximation have been around for some ti...
As devices and lines shrink into the deep submicron range, the propagation delay of signals can be e...
Abstract During the routing of global interconnects, macro blocks form useful routing regions which ...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
We describe a new algorithm for floorplan evalua-tion using timing-driven buffered routing according...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron des...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according ...
To implement high-performance global interconnect without impacting the performance of existing bloc...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
To implement high-performance global interconnect without impact-ing the performance of existing blo...
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the ...