This paper studies pseudo-random pattern testing of bridging faults. Although bridging faults are generally more random pattern testable than stuck-at faults, examples are shown to illustrate that some bridging faults can be much less random pattern testable than stuck-at faults. A fast method for identifying these random-pattern-resistant bridging faults is described. It is shown that state-of-the-art test point insertion techniques, which are based on the stuck-at fault model, are inadequate. Data is presented which indicates that even after inserting test points that result in 100 % single stuck-at fault coverage, many bridging faults are still not detected. A test point insertion procedure that targets both single stuck-at faults and no...
Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly ...
A novel algorithm for diagnosing all two-line single bridging faults in combinational circuits is pr...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...
If a test set for more complex faults than stuck-at faults is generated, higher defect coverage woul...
An ATPG for resistive bridging faults is proposed that combines the advantages of section-based gene...
International audienceThe combination of higher quality requirements and sensitivity of high perform...
A new testing paradigm called Built-In Self-Test (BIST) has been gaining increasing acceptance over ...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on resee...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
An automated logic synthesis procedure, called RP-SYN, is described for synthesizing random pattern ...
Download Citation Email Print Request Permissions Feedback bridging faults may giv...
The test pattern generator produces test vectors that are applied to the tested circuit during pseu...
As the complexity of current hardware systems rises, it is challenging to harden these systems again...
Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnos...
Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly ...
A novel algorithm for diagnosing all two-line single bridging faults in combinational circuits is pr...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...
If a test set for more complex faults than stuck-at faults is generated, higher defect coverage woul...
An ATPG for resistive bridging faults is proposed that combines the advantages of section-based gene...
International audienceThe combination of higher quality requirements and sensitivity of high perform...
A new testing paradigm called Built-In Self-Test (BIST) has been gaining increasing acceptance over ...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on resee...
[[abstract]]During built-in self-test (BIST), the set of patterns generated by a pseudo-random patte...
An automated logic synthesis procedure, called RP-SYN, is described for synthesizing random pattern ...
Download Citation Email Print Request Permissions Feedback bridging faults may giv...
The test pattern generator produces test vectors that are applied to the tested circuit during pseu...
As the complexity of current hardware systems rises, it is challenging to harden these systems again...
Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnos...
Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly ...
A novel algorithm for diagnosing all two-line single bridging faults in combinational circuits is pr...
The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances...