BDD-based logic synthesis for LUT-based FPGAs

Contemporary FPGA synthesis is a multi-phase process which involves technology independent logic optimization followed by FPGA-specific mapping to a target FPGA technology. Conventional technology-independent transformations target standard cells and are unable to optimize circuits with constraints and goals specific to FPGA architectures. This paper describes an FPGAspecific logic synthesis approach,which unites multi-level logic transformation,decomposition,and optimization techniques into a single synthesis framework. This system performs network transformation,decomposition and optimization at an early stage to generate a network which can be directly mapped onto FPGAs. Our techniques are built upon a BDD-based logic decomposition system. With this system,both AND-OR decompositions and AND-XOR decompositions can be identified,resulting in large area savings for synthesized XOR-intensive circuits. To induce good decompositions,a maximum fanout free cone (MFFC) based partial clustering and collapsing technique is used. This step is followed by an area-minimizing variable partitioning heuristic which decomposes collapsed nodes into LUT-feasible sub-functions. As a post-processing step,a performance-driven re-synthesis phase is performed to alleviate increased delay caused by excessive logic sharing. We compare the quality of results obtained using our techniques with thos