The Effect of First-Level Cache Improvements on the RAMpage Memory Hierarchy

The RAMpage memory hierarchy is an alternative memory organization which addresses the growing CPU-DRAM speed gap, by replacing the lowest-level cache by an SRAM main memory. This paper presents some modifications to the RAMpage hierarchy to enhance its performance. More aggressive first level cache implementations were shown to improve performance of the RAMpage model, when context switches were taken on misses to DRAM. The results strengthen the case for the feasibility of the RAMpage model as a viable alternative to the conventional memory organisation