Coordinated power, energy, and temperature management for highperformance processors

High-performance desktop and server processor design is hampered by constraints on chip power, temperature, and energy. We have investigated dynamic power characteristics of high-performance pipelines and static energy management techniques for large on-chip caches in previous work. Our analysis indicates that a large portion of the power budget is devoted to overhead, spending power to achieve incremental performance improvements. Existing approaches to managing both static and dynamic energy have proven useful but have room for improvement as the ratio of cost to benefit shifts with increased power liability per transistor in future processor generations. In response, we are currently developing a coordinated microprocessor manager that enables high performance throughout a wide range of throughput, power, energy, and temperature targets for the next generation of processor designs. In addition to budgeting dynamic power, the manager will coordinate leakage control mechanisms and balance resource activity levels to avoid thermal emergencies due to hot spots on die. This report summarizes the foundations of this work and our current status in this endeavor.