A Complementary GaAs Microprocessor for Space Applications

Abstract—This paper describes the development of a complementary GaAs PowerPC TM microprocessor suitable for space applications. Motorola’s 0.5μm Complementary GaAs (CGaAs TM) process was selected as the semiconductor technology because of its unique abilities to meet the requirements of space and satellite systems. Recently published findings indicate that CGaAs has a power-delay product of 0.01 μW/MHz/gate. Additionally, the CGaAs process is resistant to single-event upset (SEU) (10-9 to 10-10 upsets/bit-day), total dose radiation (10 8 rads), and latchup. These properties make CGaAs attractive for space and satellite applications. However, CGaAs presents design challenges such as reduced power-supply voltage, gate leakage, subthreshold drain-source leakage, and low integration level, all of which impact digital circuits. The processor architecture described in this paper is driven by the constrained integration level. Architectural simulations reveal that an acceptable level of performance can be reached by efficiently utilizing the resources available. The processor implements a small on-chip primary instruction cache and a larger off-chip primary data cache. The instruction fetch mechanism is guided by a small two-level dynamic branch prediction mechanism. Computation is performed by a small superscalar execution core. The architecture, running at 200MHz, is capable of achieving 153 MIPS, translating to a 27 % performance increase over a comparable traditional pipelined microprocessor. Researchers at the University of Michigan have designed a prototype CGaAs 32-bit PowerPC microprocessor based on this architecture, which is now being fabricated. This paper will summarize the advantages and design challenges of developing a radiation-hard CGaAs microprocessor. The constraints and limitations of the technology as they affect system architecture will be discussed. Architectural features that improve the performance of the processor despite the limited integration levels will be presented. I