Early Stage Microarchitectural Design for Lifetime Reliability srinivsn,sadve ¡ pbose,jarivers¡

Submitted for publication. Please do not distribute. Although device scaling has been providing steady increases in processor performance, it has also led to higher processor hard error failure rates. Increased power densities (and resultant temperatures) and other effects of scaling are predicted to cause significant lifetime reliability problems in the near future. In this paper, we examine microarchitectural design time enhancements for processor reliability. Specifically, we study two techniques which introduce structural redundancy into the processor for reliability enhancement. First, in structural duplication, redundant microarchitectural structures are added to the processor and designated as spares. Spare structures can be turned on when the original structure fails, increasing the processor’s lifetime. We also propose a new run-time technique, graceful processor degradation, which allows the processor to exploit existing microarchitectural redundancy by shutting down failed structures while still maintaining functionality, thereby increasing the processor’s lifetime. Our analysis shows that early design time techniques can provide significant reliability benefits, and we present guidelines for the optimal usage of these techniques by identifying situations where each is more beneficial. We show that graceful processor degradation is the superior technique when only limited performance or area resources can be sacrificed for reliability. Specifically, on average, graceful processor degradation can deliver a 39 % increase in reliability for only a 5 % loss in performance. On the other hand, for systems where reliability is more important than performance or area, structural duplication is more beneficial. Structural duplication can use a 100 % area overhead to increase processor reliability by as much as 224 % on average. 1