Near-optimal critical sink routing tree constructions

Abstract-We present critical-sink routing tree (CSRT) con-structions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and “global slack removal ” algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67 %) over minimum Steiner routings in terms of delays to identified critical sinks. ERT’s also serve as generic high-performance routing trees when no critical sink is specified: for 8-sink nets in standard IC (MCM) technology, we improve average sink delay by 19