Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)

In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switching technique and its routing algorithm is livelock-/deadlock- free in 2D-mesh topology. Major contribution of this research is the design of an adaptive router architecture adopting a minimal adaptive routing algorithm with near optimal performance and feasible design complexity, satisfying the general SoC design requirements. We also investigate the optimal size of FIFO in an adaptive router with fixed priority scheme.