Abstract. Alias analysis, traditionally performed statically, is unsuited for a dynamic binary translator (DBT) due to incomplete control-flow information and the high complexity of an accurate analysis. Whole- program profiling, however, shows that most memory references do not alias. The current technique used in DBTs to disambiguate memory references, instruction inspection, is too simple and can only disambiguate one-third of potential aliases. To achieve effective memory disambiguation while keeping a tight bound on analysis overhead, we propose an efficient heuristic algorithm that strategically selects key memory dependences to disambiguate with runtime checks. These checks have little runtime overhead and, in the common case where a...
This paper evaluates three alias analyses based on programming language types. The first analysis us...
As one optimization technique used in the static analysis of compilers, alias analysis has been deve...
Recently, CPUs with an identical ISA tend to have different microarchitectures, different computatio...
Hardware accelerators are an energy efficient alternative to general purpose processors for specific...
This paper evaluates three alias analyses based on program-ming language types. The first analysis u...
High-performance architectures rely upon powerful optimizing and parallelizing compilers to maximize...
In this paper, an implementation of a demand-driven alias analysis [7] in Open64 is presented. In th...
Trace scheduling is a global compaction technique for transforming sequential programs into paralle...
Recently, reconfigurable architectures, which outperform DSP processors, have become important. Alth...
This paper evaluates three alias analyses based on programming language types. The first analysis us...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
Dynamic binary translators (DBTs) are becoming increas-ingly important because of their power and fl...
International audienceIn order to optimize code effectively, compilers must deal with memory depende...
Dynamic binary translators (DBTs) provide powerful platforms for building dynamic program monitoring...
This paper evaluates three alias analyses based on programming language types. The first analysis us...
As one optimization technique used in the static analysis of compilers, alias analysis has been deve...
Recently, CPUs with an identical ISA tend to have different microarchitectures, different computatio...
Hardware accelerators are an energy efficient alternative to general purpose processors for specific...
This paper evaluates three alias analyses based on program-ming language types. The first analysis u...
High-performance architectures rely upon powerful optimizing and parallelizing compilers to maximize...
In this paper, an implementation of a demand-driven alias analysis [7] in Open64 is presented. In th...
Trace scheduling is a global compaction technique for transforming sequential programs into paralle...
Recently, reconfigurable architectures, which outperform DSP processors, have become important. Alth...
This paper evaluates three alias analyses based on programming language types. The first analysis us...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
To expose sufficient instruction-level parallelism (ILP) to make effective use of wide-issue supersc...
Dynamic binary translators (DBTs) are becoming increas-ingly important because of their power and fl...
International audienceIn order to optimize code effectively, compilers must deal with memory depende...
Dynamic binary translators (DBTs) provide powerful platforms for building dynamic program monitoring...
This paper evaluates three alias analyses based on programming language types. The first analysis us...
As one optimization technique used in the static analysis of compilers, alias analysis has been deve...
Recently, CPUs with an identical ISA tend to have different microarchitectures, different computatio...