Hierarchical Whitespace Allocation in Top-down Placement

Increased transistor density in modern commercial ICs typically originates in new manufacturing and defect prevention technologies [13, 14]. Additionally, better utilization of such low-level transistor density may result from improved software that makes fewer assumptions about physical layout in order to reliably automate the design process. We observe that existing block- and chip-level layout instances can have considerable amounts of whitespace { i.e., deliberately unused, costly layout area { in order to reliably produce high-quality automatic layout solutions. Indeed, modern designs typically have from several percent up to 20 % or more whitespace [5]. Whitespace can be the result of several phenomena, including pin-limited designs, limits of power distribution/dissipation density, and the need to maintain autoroutability. The rst two of these phenomena are intrinsic to the design; the third is the result of limits in the place-and-route tools. A fourth cause of whitespace, also due to tool limitations, is the use of move-based hypergraph partitioning in top-down placement of standard-cell row-based designs. As the partitioning tolerance decreases in the partitioning instance, the results of modern hypergraph partitioners (cutsize, and the ability to nd a solution that meets balance constraints) deteriorate signi cantly [7]. Partitionin