Fast Comparisons of Circuit Implementations

Abstract — Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing can significantly improve circuit performance, by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs, are not known prior to sizing. In this paper, we present two metrics for comparing different implementations – the minimum achievable delay, and the cost of achieving a target delay, and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the trade-offs between multiple functionally identical implementations, and has to size only the selected implementation. Index Terms — Estimation, Very-large-scale integration, CMOS digital integrated circuits, Digital integrated circuit