QUICK PIPING: A Fast, High-Level Model for Describing Processor Pipelines †

Responding to marketplace needs, today’s embedded processors must feature a flexible core that allows easy modification with fast time to market. In this environment, embedded processors are increasingly reliant on flexible support tools. This paper presents one such tool, called Quick Piping, a new, high-level formalism for modeling processor pipelines. Quick Piping consists of three primary components that together provide an easy-to-build, reusable processor description: Pipeline graphs—a new high-level formalism for modeling processor pipelines, pipe—a companion domain-specific language for specifying a pipeline graph, pipe miner—a compiler specification generator for pipe descriptions. pipe miner processes a pipe description and produces a compiler specification that is used to build a compiler that reads the corresponding machine’s instruction set and automatically generates resource vectors. Despite their ubiquity and importance in achieving high performance in modern processors, pipelines—and improving the mechanisms for specifying their operation—have received little attention. Until now, handwritten resource vectors have served to specify information about a processor’s pipeline and encode relevant information about each instruction’s resource usage. Describing the complete set of resource vectors for a machine can be quite tedious and error prone, since it commonly must be developed by hand on an instruction-by-instruction basis. With its use of pipeline graphs, the pipe language, and the pipe miner compiler specification generator, Quick Piping gives the embedded processor architect and compiler writer an intuitive high-level abstraction of pipelines, a language for specifying a pipeline, and a tool for automatically producing pipeline resource vectors. The resulting specifications are quick to develop, easy to understand, simple to modify and maintain, and can be automatically processed to produce the low-level information required by processor control units and instruction schedulers