Speed and Noise Immunity Enhanced Low Power Dynamic Circuits

Abstract – Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the subthreshold leakage energy of domino logic circuits. A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60 % while reducing power dissipation by 35 % as compared to a standard domino logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a standard domino circuit. The proposed domino logic circuit technique offers 14 % higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a standard domino circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced. A low swing domino logic technique is proposed to decrease the dynamic switching power without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4 % as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be furthe