Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques

The explosive growth of Internet traffic has created an acute demand for networks of ever increasing throughput. Besides raw throughput, modern mutlimedia applications also demand Quality of Service (QoS) guarantees. Both of these requirements result in a new generation of switches and routers, which use specialized hardware to support high speeds and advanced QoS. This thesis studies one of the subsystems of such switches/routers, namely queue management in the ingress and egress line cards at OC-192 (10 Gbps) line rate. The provision of QoS guarantee usually requires flow isolation, which is often achieved using per-flow queueing. The implementation of a queue manager, supporting thousands of flows and operating at such high speed, is challenging. We study thoroughly this issue and we show that the queue manager implementation is feasible by using advanced hardware techniques, similar to those employed in the supercomputers of the 60's and in modern microprocessors. We use DRAM technology for buffer memory in order to provide large buffer space. To effectivel