As the integrated circuits (ICs) are scaled into nanometer dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. This paper presents the ongoing research effort at UCLA in developing an interconnect-centric design flow, including interconnect planning, interconnect synthesis, and interconnect layout, which allows interconnect design and optimization to be properly considered at every level of the design process. Efficient interconnect performance estimation models and tools at various levels are also developed to support such an interconnect-centric design flow. Keywords—Buffer block planning, buffer insertion, circuit partitioning, computer-aided design, delay...
It is widely accepted that, as semiconductor technology continues to evolve, interconnects have domi...
The scaling of integrated circuit (IC) technologies to the nanometer regime has resulted in various ...
In recent times, even small improvements in performance and power are seen as huge wins in digital i...
Interconnect has become the dominating factor in determining circuit performance and reliability in ...
This book covers layout design and layout migration methodologies for optimizing multi-net wire stru...
As Moore’s law is followed closely over the past decades, down-scaling of transistor structure lea...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
As we approach serious scaling roadblocks in the next few process nodes, it is imperative to identif...
The objective of this research is to present a holistic study of the on-chip copper interconnect tec...
In nanometer designs, interconnect delay dominates the overall circuit delay, and hence design focus...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
This paper presents an overview of recent advances on modeling and layout optimization of devices an...
The goals of the work presented in this paper were to estimate quantitatively the impact of intercon...
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very La...
The advent of the nanotechnology has introduced new challenges and non-conventional problems to high...
It is widely accepted that, as semiconductor technology continues to evolve, interconnects have domi...
The scaling of integrated circuit (IC) technologies to the nanometer regime has resulted in various ...
In recent times, even small improvements in performance and power are seen as huge wins in digital i...
Interconnect has become the dominating factor in determining circuit performance and reliability in ...
This book covers layout design and layout migration methodologies for optimizing multi-net wire stru...
As Moore’s law is followed closely over the past decades, down-scaling of transistor structure lea...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
As we approach serious scaling roadblocks in the next few process nodes, it is imperative to identif...
The objective of this research is to present a holistic study of the on-chip copper interconnect tec...
In nanometer designs, interconnect delay dominates the overall circuit delay, and hence design focus...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
This paper presents an overview of recent advances on modeling and layout optimization of devices an...
The goals of the work presented in this paper were to estimate quantitatively the impact of intercon...
This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very La...
The advent of the nanotechnology has introduced new challenges and non-conventional problems to high...
It is widely accepted that, as semiconductor technology continues to evolve, interconnects have domi...
The scaling of integrated circuit (IC) technologies to the nanometer regime has resulted in various ...
In recent times, even small improvements in performance and power are seen as huge wins in digital i...