Hierarchical Fault Simulation in Digital Systems

A new method for hierarchical fault simulation based on multilevel Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for blocks of the RTL structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows to reduce time expenses in the comparison to traditional gate-level fault simulation approach. This is reflected in the experimental results. 1