Cache-line decay: A mechanism to reduce cache leakage power

Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we explore an architectural idea to reduce leakage power in data caches. Previous work has shown that cache frames are “dead ” for a significant fraction of time [14]. We are exploiting this observation to turn off cache lines that are not likely to be accessed anymore. Our method is simple: if a cacheline is not accessed within a fixed interval (called decay interval) we turn off its supply voltage using a gated V dd technique introduced previously [1]. We study the effect of cache-line decay on both power consumption and performance. We find that it is possible with cache-line decay to build larger caches that dissipate less leakage power than smaller caches while yielding equal or better performance (fewer misses). In addition, because our method can dynamically trade performance for leakage power it can be adjusted according to the requirements of the application and/or the environment.