Abstract Validation of an Architectural Level Power Analysis Technique

This paper presents a technique used to dopower analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP anda32-bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instruction/data ow stream. We demonstrate the accuracy of the estimator by comparing the power values it produces against measurements made by agate level power simulator for the same benchmark set. Our estimation approach has been shown to provide very e cient, accurate power analysis at the architectural level.