Modern processors attempt to overcome increasing memory latencies by anticipating future references and prefetching those blocks from memory. The behavior and possible negative side effects of prefetching schemes are fairly well understood for uniprocessor systems. However, in a multiprocessor system a prefetch can steal read and/or write permissions for shared blocks from other processors, leading to permission thrashing and overall performance degradation. In this paper, we present a taxonomy that classifies the effects of multiprocessor prefetches. We also present a characterization of the effects of four different hardware prefetching schemes--sequential prefetching, content-directed data prefetching, wrong path prefetching and exclusiv...
High performance processors employ hardware data prefetching to reduce the negative performance impa...
Journal PaperCurrent microprocessors incorporate techniques to aggressively exploit instruction-leve...
Abstract Data prefetching is an effective data access latency hiding technique to mask the CPU stall...
Compiler-directed cache prefetching has the poten-tial to hide much of the high memory latency seen ...
Data prefetching has been widely studied as a technique to hide memory access latency in multiproces...
A major performance limiter in modern processors is the long latencies caused by data cache misses. ...
Prefetching is an important technique for reducing the average latency of memory accesses in scalabl...
International audienceIn multi-core systems, an application's prefetcher can interfere with the memo...
Prefetching, i.e., exploiting the overlap of processor com-putations with data accesses, is one of s...
Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle trad...
Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems...
Abstract As the difference in speed between processor and memory system continues to increase, it is...
Data prefetching has been considered an effective way to mask data access latency caused by cache mi...
Current microprocessors aggressively exploit instruction-level parallelism (ILP) through techniques ...
This paper presents new analytical models of the performance be-nefits of multithreading and prefetc...
High performance processors employ hardware data prefetching to reduce the negative performance impa...
Journal PaperCurrent microprocessors incorporate techniques to aggressively exploit instruction-leve...
Abstract Data prefetching is an effective data access latency hiding technique to mask the CPU stall...
Compiler-directed cache prefetching has the poten-tial to hide much of the high memory latency seen ...
Data prefetching has been widely studied as a technique to hide memory access latency in multiproces...
A major performance limiter in modern processors is the long latencies caused by data cache misses. ...
Prefetching is an important technique for reducing the average latency of memory accesses in scalabl...
International audienceIn multi-core systems, an application's prefetcher can interfere with the memo...
Prefetching, i.e., exploiting the overlap of processor com-putations with data accesses, is one of s...
Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle trad...
Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems...
Abstract As the difference in speed between processor and memory system continues to increase, it is...
Data prefetching has been considered an effective way to mask data access latency caused by cache mi...
Current microprocessors aggressively exploit instruction-level parallelism (ILP) through techniques ...
This paper presents new analytical models of the performance be-nefits of multithreading and prefetc...
High performance processors employ hardware data prefetching to reduce the negative performance impa...
Journal PaperCurrent microprocessors incorporate techniques to aggressively exploit instruction-leve...
Abstract Data prefetching is an effective data access latency hiding technique to mask the CPU stall...