We present LEOPARD, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries. Our algorithm minimizes area under required timing and input capacitance constraints by finding the tree topology and assigning different gains to each buffer to minimize the total buffer area. Experimental results show that the new algorithm achieves significant buffer area improvement compared to previous approaches. 1
This document presents a multi-objective approach to buffer insertion. Our concept is applied to sim...
Restricted until 3 Mar. 2010.As semiconductor technology advances into smaller and smaller geometrie...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
This paper presents LEOPARD, a Logical Effort-based fanout OPtimizer for ARea and Delay, which relie...
In this paper we present a new fanout optimization algorithm which is particularly suitable for digi...
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the tim...
In production lines, buffers function as a means to decouple stations, which reduce the effect that ...
We study integrated prefetching and caching problems following the work of Cao et. al. [3] and Kimbr...
Abstract- As gate delays decrease faster than wire delays for each technology generation, buffer ins...
This paper addresses the problem of low-power fanout optimization with multiple threshold voltage in...
We study integrated prefetching and caching problems following the work of Cao et al. [1995] and Kim...
International audienceOptimizing digital designs implies a selection of circuit implementation based...
Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however...
This paper presents an integrated approach to solve the buffer allocation problem in unreliable prod...
[[abstract]]Conventional studies on buffer-constrained flowshop scheduling problems have considered ...
This document presents a multi-objective approach to buffer insertion. Our concept is applied to sim...
Restricted until 3 Mar. 2010.As semiconductor technology advances into smaller and smaller geometrie...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
This paper presents LEOPARD, a Logical Effort-based fanout OPtimizer for ARea and Delay, which relie...
In this paper we present a new fanout optimization algorithm which is particularly suitable for digi...
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the tim...
In production lines, buffers function as a means to decouple stations, which reduce the effect that ...
We study integrated prefetching and caching problems following the work of Cao et. al. [3] and Kimbr...
Abstract- As gate delays decrease faster than wire delays for each technology generation, buffer ins...
This paper addresses the problem of low-power fanout optimization with multiple threshold voltage in...
We study integrated prefetching and caching problems following the work of Cao et al. [1995] and Kim...
International audienceOptimizing digital designs implies a selection of circuit implementation based...
Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however...
This paper presents an integrated approach to solve the buffer allocation problem in unreliable prod...
[[abstract]]Conventional studies on buffer-constrained flowshop scheduling problems have considered ...
This document presents a multi-objective approach to buffer insertion. Our concept is applied to sim...
Restricted until 3 Mar. 2010.As semiconductor technology advances into smaller and smaller geometrie...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...