System level modeling is becoming a necessity in all areas of engineering design. As systems grow in complexity, designers may increasingly rely on commercial off-the-shelf (COTS) components. Frequently, these components are described at a high level of abstraction (behaviorally) that complicates fault testing. This paper discusses the trade-offs of using behavioral components in a design, specifically as it relates to fault simulation. We investigate important issues such as timing, and examine the need to internally fault behavioral models. We then present our multi-level concurrent fault simulator (MCS) that can accept any combination of gate level and behavioral models using a single kernel. Our kernel propagates faults through behavior...
This paper presents measurements obtained while performing fault simulations of MOS circuits modeled...
94 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987.The goals of this thesis are t...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
Discrete event modeling allows designing an easy-to-handle and reusable represen-tation of a system ...
Abstract—This paper provides a methodology that leverages state-of-the-art techniques for efficient ...
The Concurrent and Comparative Simulation (CCS) allows several simulations on a system in one single...
This paper provides a methodology that leverages state-of-the-art techniques for efficient fault sim...
In recent technology nodes, reliability is increasingly considered a part of the standard design flo...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
Fault injection is widely used for validating dependability of computer systems. These techniques ha...
This paper presents measurements obtained while performing fault simulations of MOS circuits modeled...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
The growing size and complexity of VLSI circuits is creating a need for more efficient design automa...
This paper presents measurements obtained while performing fault simulations of MOS circuits modeled...
94 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987.The goals of this thesis are t...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
Discrete event modeling allows designing an easy-to-handle and reusable represen-tation of a system ...
Abstract—This paper provides a methodology that leverages state-of-the-art techniques for efficient ...
The Concurrent and Comparative Simulation (CCS) allows several simulations on a system in one single...
This paper provides a methodology that leverages state-of-the-art techniques for efficient fault sim...
In recent technology nodes, reliability is increasingly considered a part of the standard design flo...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
Fault injection is widely used for validating dependability of computer systems. These techniques ha...
This paper presents measurements obtained while performing fault simulations of MOS circuits modeled...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...
The growing size and complexity of VLSI circuits is creating a need for more efficient design automa...
This paper presents measurements obtained while performing fault simulations of MOS circuits modeled...
94 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987.The goals of this thesis are t...
In this paper, a hierarchical fault simulation technique for neural networks is proposed, supporting...