The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled interconnections strongly de-pends upon the signal activity. A transient analysis of two capaci-tively coupled CMOS logic gates is presented in this paper for dif-ferent combinations of signal activity, The uncertainty of the ef-fective load capacitance and propagation delay due to the signal activity is addressed. Analytical expressions characterizing the out-put voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3 % as compared to SPICE, while the estimated delay neglecting the difference between the load ca-pacitances can exceed 45%. T...
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock fre...
With the continued scaling of CMOS VLSI, power dissipation of logic circuits has increasingly come t...
Continuous semiconductor technology scaling has brought the digital circuit noise problem to the for...
The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled inte...
The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gat...
Abstract—On-chip parasitic inductance inherent to the power distribution network has becoming signif...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Continuous scaling of high performance CMOS circuits creates a plethora of noise/reliability effects...
Abstmct- Interconnect between a CMOS driver and re-ceiver can be modeled as a lossy transmission lin...
We present a noise-driven effective capacitance method for estimating the combined propagation noise...
Abstract—In this paper we propose a dynamic noise model to verify functional failures due to crossta...
While estimating glitches or spurious transitions is challenge due to signal correlations, the rando...
In this paper, the modeling of CMOS SCL gates is addressed. The topology both with and without outpu...
The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. ...
While estimating glitches or spurious transitions is challenge due to signal correlations, the rando...
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock fre...
With the continued scaling of CMOS VLSI, power dissipation of logic circuits has increasingly come t...
Continuous semiconductor technology scaling has brought the digital circuit noise problem to the for...
The effect of interconnect coupling capacitance on neighboring CMOS logic gates driving coupled inte...
The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gat...
Abstract—On-chip parasitic inductance inherent to the power distribution network has becoming signif...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Continuous scaling of high performance CMOS circuits creates a plethora of noise/reliability effects...
Abstmct- Interconnect between a CMOS driver and re-ceiver can be modeled as a lossy transmission lin...
We present a noise-driven effective capacitance method for estimating the combined propagation noise...
Abstract—In this paper we propose a dynamic noise model to verify functional failures due to crossta...
While estimating glitches or spurious transitions is challenge due to signal correlations, the rando...
In this paper, the modeling of CMOS SCL gates is addressed. The topology both with and without outpu...
The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. ...
While estimating glitches or spurious transitions is challenge due to signal correlations, the rando...
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock fre...
With the continued scaling of CMOS VLSI, power dissipation of logic circuits has increasingly come t...
Continuous semiconductor technology scaling has brought the digital circuit noise problem to the for...
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