Resource widening versus replication: limits and performance-cost trade-off

A balanced increase of memory bandwidth and computational capabilities is going to be one of the trends in the design of near future high-performance microprocessors. Alternative solutions are foreseen for the organization of their resources, mainly based on different degrees of resource replication and/or adaptation of resources to the most frequently found operations in highly performance demanding applications. For instance, doubling the width of buses between the register file and the first-level data cache is an example of design that attains similar performance results than doubling the number of buses in numerical applications. In this paper we evaluate the cost/performance trade-off of a wide set of design alternatives oriented towards having high memory bandwidth and computing capabilities in future architectures. Different degrees of resource replication and widening are the basis for the generation of the design space. Performance evaluation is based on the results obtained for a large number of inner loops in the Perfect Club benchmarks. Implementation costs for the register file and functional units are estimated for different foreseen integration technologies which allow us to analyse their future availability. The results show that replicating is most effective in terms performance but results in an unafordable cost while widening has a much smaller cost but less performance. Combining a small degree of widening and replication results in the best performance/cost ratio. 1