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4 It is well known that the success of VLIW is ascribed to keep the hardware simple and transparent tothe compiler. Though state-of-the-art VLIW compilers utlize the resource latency and utilization information in crafting highly optimized instruction schedules, they can be still improved. Typically forwardingcircuitry and pipeline registers are not transparent to compiler, essentially due to interruption handling mechanisms. The aim of this project is to study the potential savings in power/energy possible by makingthe aforementioned resources transparent to the compiler