Improving Power Efficiency in Stream Processors Through Dynamic Reconfiguration

Stream processors support hundreds of functional units in a programmable architecture by clustering those units and utilizing a bandwidth hierarchy. This paper presents mechanisms to enable dynamic reconfiguration of the number of clusters in a stream processor to match the time varying data parallelism of an application. Many embedded applications go through several phases of execution, marked by changes in the level of available parallelism. While the level of parallelism within each phase is determined by runtime parameters, the compiler is aware of when these phase changes can occur. To efficiently adapt to these application phases, we introduce three compiler controlled reconfiguration mechanisms which allow the number of clusters, number of functional units, frequency, and voltage to be varied dynamically, improving the power efficiency of the architecture. A 32-user wireless basestation is a prime example of a workload that benefits from such reconfiguration. When the number of users supported by the basestation dynamically changes from 32 to 4, the reconfiguration from a 32-cluster stream processor to a 4-cluster stream processor yields an additional 15–85 % power savings over a stream processor with dynamic voltage and frequency scaling alone.