THIS OPEN-SOURCE INTEGRATED SIMULATION INFRASTRUCTURE CONTAINS A CYCLE-ACCURATE SIMULATOR FOR A TYPICAL NETWORK PROCESSOR ARCHITECTURE, AN AUTOMATIC VERIFICATION FRAMEWORK FOR TESTING AND VALIDATION, AND A POWER ESTIMATION MODEL FOR MEASURING THE

Network processors recently emerged as a successful platform providing both high performance and flexibility in building powerful routers. A typical network processor (NP) includes multiple fast-execution cores on a single chip that exploits packet-level parallelism. Example products include Intel’s IXP family, 1 IBM’s PowerNP, Motorola’s C-Port, and Agere’s APP550. With the exponential increase in clock frequency and core complexity, power dissipation will become a major design consideration in NP development. For example, a typical router configuration might include one or two NPs per line card. A group of line cards, say 16 or 32, generally reside