EMBEDDED DETERMINISTIC TEST FOR SYSTEMS-ON-A-CHIP BY

ii Embedded deterministic test (EDT) is a manufacturing test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deter-ministic stimuli inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low cost testers for rapidly achieving high fault coverage, EDT must consciously use the available tester channels to ensure non-disruptive scaling to future devices of increased complexity. The focus of this thesis is to introduce a new EDT approach for systems-on-a-chip (SOCs) that are designed using embedded cores that are intellectual property (IP)-protected. Following an introduction to integrated circuit testing and an overview of the related work, we define the criteria that must be satisfied by the EDT approaches for the future SOCs of ever growing complexity. Then we observe that the necessary amount of compressed volume of test data transferred from the tester to the embedded cores in an SOC varies significantly during the testing process. This motivates