The CMOS IC industry thrives on the down-scaling drive for ever smaller transistors, leading to faster, smaller and more complex digital systems. These ICs are interconnected by electrical tracks running on Printed Circuit Boards. Due to different frequency-dependent sources of signal degradation, the performance of these electrical interconnects lags behind the IC performance. As the electrical interconnect bottleneck increasingly impacts overall system performance, the interest in optical interconnects at the inter-chip level is growing. An important question to answer is how and where such optical interconnects should be implemented. Therefore, we first discuss the weaknesses of electrical interconnects and the potential benefits of opti...
Optical interconnect is claimed to have signi¯cant advantages over electrical interconnect due to th...
Centimeter-range high-density optical interconnect between chips is coming into reach with current o...
The performance of future generation data processing systems will be set by interconnect limitations...
The various arguments for introducing optical interconnections to silicon CMOS chips are summarized,...
The performance of future data processing systems will be set by interconnection limitations rather ...
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasing...
This paper discusses short-distance optical interconnects for general-purpose distributed digital sy...
Electrical interconnects are becoming a bottleneck in the way towards meeting future performance req...
Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is sca...
Chip I/O pins are an increasingly limited resource and significantly affect the performance, power a...
The evolution of integrated circuit technology is causing system designs to move towards communicati...
We propose a simple, low cost, parallel optical data bus for CMOS to CMOS optical interconnects. At ...
Super computing is reaching out to ExaFLOP processing speeds, creating fundamental challenges for th...
This paper describes a complete technology family for parallel optical interconnect systems. Key fea...
Abstract-The evolution of integrated circuit technology is causing system designs to move towards co...
Optical interconnect is claimed to have signi¯cant advantages over electrical interconnect due to th...
Centimeter-range high-density optical interconnect between chips is coming into reach with current o...
The performance of future generation data processing systems will be set by interconnect limitations...
The various arguments for introducing optical interconnections to silicon CMOS chips are summarized,...
The performance of future data processing systems will be set by interconnection limitations rather ...
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasing...
This paper discusses short-distance optical interconnects for general-purpose distributed digital sy...
Electrical interconnects are becoming a bottleneck in the way towards meeting future performance req...
Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is sca...
Chip I/O pins are an increasingly limited resource and significantly affect the performance, power a...
The evolution of integrated circuit technology is causing system designs to move towards communicati...
We propose a simple, low cost, parallel optical data bus for CMOS to CMOS optical interconnects. At ...
Super computing is reaching out to ExaFLOP processing speeds, creating fundamental challenges for th...
This paper describes a complete technology family for parallel optical interconnect systems. Key fea...
Abstract-The evolution of integrated circuit technology is causing system designs to move towards co...
Optical interconnect is claimed to have signi¯cant advantages over electrical interconnect due to th...
Centimeter-range high-density optical interconnect between chips is coming into reach with current o...
The performance of future generation data processing systems will be set by interconnect limitations...