Synthesizing Asynchronous Micropipelines with Design Compiler

We present an asynchronous micropipeline synthesis flow supporting conventional synthesizable HDL specifications. Using Synopsys Design Compiler as the front-end interfacing behavior specification, the synthesis core and the final netlist front-end ensures easy integration into conventional design flow. With our RTL to micropipeline re-implementation engine in the backend, conventional HDL specification is implemented as an asynchronous micropipeline. Synthesis can be targeted at a wide range of micropipeline protocols and implementations through standard cell library approach. Primary target applications include high throughput low power using domino-like low-latency cells and designs requiring side channel attack resistance using a power balanced micropipeline library