An Architecture Description Language for Massively Parallel Processor Architectures

In this paper, we introduce an architecture description language for modeling, simulation, and evaluation of massively parallel processor architectures that are designed for special purpose applications from the domain of embedded systems. The architectural description of the processor system is supposed to be done according to two abstraction levels. Architectural parameters of processor elements are characterized on processor level and the interaction between processors (i.e., interconnect topology, positioning of the processors, etc.) is described on the array level. Key features, semantic, and technical innovations of the proposed architecture description language are demonstrated in this paper