Performance of Systems

Thread-Level Data Speculation (TLDS) is a technique which enables the optimistic parallelization of applications despite ambiguous data dependences between the resulting threads. Although TLDS is mostly managed by software, hardware provides two key pieces of functionality: (i) detecting dependence violations, and (ii) bu ering speculative side-e ects until they can be safely committed to memory. To provide this functionality we present an extension to invalidation-based cache coherence which is both scalable and has a minimal impact on hardware complexity. We explore the design space in depth and nd that our baseline architecture is su cient to exploit speculative parallelism