As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by deep-submicron technologies can be alleviated by using a multiple voltage/multiple frequency island design style, or otherwise called, globally asynchronous, locally synchronous (GALS) design paradigm. This paper proposes a clustered architecture that enables applicationadaptive energy efficiency through the use of dynamic voltage scaling for application code that is rendered non-critical for the overall performance, at run-time. As opposed to task scheduling using dynamic voltage scaling (DVS) that exploits workload variations across applications, our approach target...
Conference of 39th European Solid-State Circuits Conference, ESSCIRC 2013 ; Conference Date: 16 Sept...
Currently, several of the high performance processors used in a PC cluster have a DVS (Dynamic Volta...
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor ...
In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines ...
Abstract—Featured by high portability and programmability, Dynamic Voltage and Frequency Scaling (DV...
Featured by high portability and programmability, Dynamic Voltage and Frequency Scaling (DVFS) has b...
Improving the energy efficiency of processor systems-on-chip (SoCs) is key to improving the performa...
Clustered architecture processors are preferred for embedded systems because centralized register fi...
Dynamic voltage and frequency scaling (DVFS), a widely adopted technique to ensure safe thermal char...
Recently, improving the energy efficiency of HPC machines has become important. As a result, interes...
This dissertation provides a comprehensive overview of the theory and practice of Dynamic Voltage/Fr...
This dissertation provides a comprehensive overview of the theory and practice of Dynamic Voltage/Fr...
Microprocessors are traditionally designed to provide "best overall" performance across a ...
Recently, energy has become an important issue in high-performance computing. For example, low power...
Power management has become an important system design issue for both embed-ded systems and server s...
Conference of 39th European Solid-State Circuits Conference, ESSCIRC 2013 ; Conference Date: 16 Sept...
Currently, several of the high performance processors used in a PC cluster have a DVS (Dynamic Volta...
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor ...
In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines ...
Abstract—Featured by high portability and programmability, Dynamic Voltage and Frequency Scaling (DV...
Featured by high portability and programmability, Dynamic Voltage and Frequency Scaling (DVFS) has b...
Improving the energy efficiency of processor systems-on-chip (SoCs) is key to improving the performa...
Clustered architecture processors are preferred for embedded systems because centralized register fi...
Dynamic voltage and frequency scaling (DVFS), a widely adopted technique to ensure safe thermal char...
Recently, improving the energy efficiency of HPC machines has become important. As a result, interes...
This dissertation provides a comprehensive overview of the theory and practice of Dynamic Voltage/Fr...
This dissertation provides a comprehensive overview of the theory and practice of Dynamic Voltage/Fr...
Microprocessors are traditionally designed to provide "best overall" performance across a ...
Recently, energy has become an important issue in high-performance computing. For example, low power...
Power management has become an important system design issue for both embed-ded systems and server s...
Conference of 39th European Solid-State Circuits Conference, ESSCIRC 2013 ; Conference Date: 16 Sept...
Currently, several of the high performance processors used in a PC cluster have a DVS (Dynamic Volta...
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor ...