For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits for use in evaluation tools, one could consider to actually generate such circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribu...
This paper presents a tool which synthesizes timed circuits from reduced state graphs. Using timing ...
In the paper, our research activities are described briefly. In the beginning, two different methodo...
International audienceThis paper describes a new procedure for generating very large realistic bench...
For the development and evaluation of CAD-tools for partition-ing, floorplanning, placement, and rou...
Programmable logic architectures increase in capacity before commercial circuits are designed for th...
grantor: University of TorontoThe development of new architectures for Field-Programmable ...
The development of next-generation CAD tools and FPGA architectures require benchmark circuits to ex...
For the development and evaluation of CAD-tools for the layout, placement, and routing of digital d...
This paper focuses on benchmarking, which is the main experimental approach to the design method and...
This paper focuses on benchmarking, which is the main experimental approach to the design method and...
This paper describes a new procedure for generating very large realistic benchmark circuits which ar...
Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an experimental appro...
The performance and capacity of Field-Programmable Gate Arrays (FPGAs) have dramatically improved in...
International audienceOptimizing digital designs implies a selection of circuit implementation based...
This paper presents a new real-world application of evolutionary computing in the area of digital ci...
This paper presents a tool which synthesizes timed circuits from reduced state graphs. Using timing ...
In the paper, our research activities are described briefly. In the beginning, two different methodo...
International audienceThis paper describes a new procedure for generating very large realistic bench...
For the development and evaluation of CAD-tools for partition-ing, floorplanning, placement, and rou...
Programmable logic architectures increase in capacity before commercial circuits are designed for th...
grantor: University of TorontoThe development of new architectures for Field-Programmable ...
The development of next-generation CAD tools and FPGA architectures require benchmark circuits to ex...
For the development and evaluation of CAD-tools for the layout, placement, and routing of digital d...
This paper focuses on benchmarking, which is the main experimental approach to the design method and...
This paper focuses on benchmarking, which is the main experimental approach to the design method and...
This paper describes a new procedure for generating very large realistic benchmark circuits which ar...
Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an experimental appro...
The performance and capacity of Field-Programmable Gate Arrays (FPGAs) have dramatically improved in...
International audienceOptimizing digital designs implies a selection of circuit implementation based...
This paper presents a new real-world application of evolutionary computing in the area of digital ci...
This paper presents a tool which synthesizes timed circuits from reduced state graphs. Using timing ...
In the paper, our research activities are described briefly. In the beginning, two different methodo...
International audienceThis paper describes a new procedure for generating very large realistic bench...