LHA: Latency Hiding Algorithm for DRAM

Accesses to slow DRAM main memory cause significant performance degradation, even in aggressive out-of-order processors. In this paper, we present a novel "LHA" scheme capable of improving DRAM performance. LHA uses a buffer which stores the most recently used addresses and associated data, but the data is only a portion of a row of data (termed row head) stored in main memory. In a memory access, both the buffer and main memory are accessed simultaneously. If the buffer contains the address requested, the buffer provides low latency data to the processor. Meanwhile, the same row address is activated in the main memory bank corresponding to the requested address found in the buffer. In this way, the buffer is used to provide the processor with low latency, and low cost DRAM is used to increase the effectiveness of caching by extending the length of the buer line to a full DRAM page