The COMPAAN/LAURA [18] tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a Process Network in which the control is parameterized and distributed. This control is given as parameterized polytopes that are expressed in terms of pseudo-linear expressions. These expressions cannot always be mapped efficiently onto hardware as they contain multiplication and integer division operations. This obstructs the data flow through the processes. Therefore, we present in this paper the Expression Compiler that efficiently maps pseudolinear expressions onto a dedicated hardware datapath in such a way that the distributed and parameterized control nev...
International audienceThe increased capacity and enhanced features of modern FPGAs opens new opportu...
We introduce dynamic computation structures (DCS), a compilation technique to produce dynamic code f...
Reconfigurable computing, in which general purpose processor (GPP) is augmented with one or more FPG...
At Leiden Embedded Research Center (LERC), we are building a tool chain called Com-paan/Laura that a...
This paper presents the Compaan tool that automatically transforms a nested loop program written in ...
Abstract — Current emerging embedded System-on-Chip plat-forms are increasingly becoming multiproces...
Current emerging embedded System-on-Chip platforms are increasingly becoming multiprocessor archit...
Reconfigurable computers based on field programmable gate array technology allow applications to be ...
A new process-independent method for the automatic synthesis of sequencers from a path expression de...
Computer hardware keeps increasing in complexity. Software design needs to keep up with this. The ri...
A process language is presented which makes a clear distinction between temporal order and causal or...
Since the end of Dennard scaling, power efficiency is the limiting factor for large-scale computing....
An extension of Milner's CCS is presented. The language takes into account a number of resourc...
Whether for use as the final target or simply a rapid prototyping platform, programming systems cont...
We use the polyhedral process network (PPN) model of computation to program and map streaming applic...
International audienceThe increased capacity and enhanced features of modern FPGAs opens new opportu...
We introduce dynamic computation structures (DCS), a compilation technique to produce dynamic code f...
Reconfigurable computing, in which general purpose processor (GPP) is augmented with one or more FPG...
At Leiden Embedded Research Center (LERC), we are building a tool chain called Com-paan/Laura that a...
This paper presents the Compaan tool that automatically transforms a nested loop program written in ...
Abstract — Current emerging embedded System-on-Chip plat-forms are increasingly becoming multiproces...
Current emerging embedded System-on-Chip platforms are increasingly becoming multiprocessor archit...
Reconfigurable computers based on field programmable gate array technology allow applications to be ...
A new process-independent method for the automatic synthesis of sequencers from a path expression de...
Computer hardware keeps increasing in complexity. Software design needs to keep up with this. The ri...
A process language is presented which makes a clear distinction between temporal order and causal or...
Since the end of Dennard scaling, power efficiency is the limiting factor for large-scale computing....
An extension of Milner's CCS is presented. The language takes into account a number of resourc...
Whether for use as the final target or simply a rapid prototyping platform, programming systems cont...
We use the polyhedral process network (PPN) model of computation to program and map streaming applic...
International audienceThe increased capacity and enhanced features of modern FPGAs opens new opportu...
We introduce dynamic computation structures (DCS), a compilation technique to produce dynamic code f...
Reconfigurable computing, in which general purpose processor (GPP) is augmented with one or more FPG...