Performance Implications of Hard-Faults in Non-Architectural Structures

Continuous circuit and wire miniaturization increasingly exert more pressure on the computer designers to address the issue of reliable operation in the presence of hard-faults. Virtually all previous work on hard-fault reliability addresses problems that arise when a fault occurs in architectural resources, such as the register file or caches. However, hard-faults can happen in non-architectural resources, such as predictors and replacement bits. Although non-architectural hard-faults do not affect correctness they can degrade a processor performance significantly and, therefore, may render them as important to deal with as architectural hard-faults. In this paper we determine, using previously proposed hard-fault models, the temperature conditions for which the frequency of hard-faults in non-architectural structures is in the same order of magnitude as in architectural structures. Furthermore, this paper quantifies the performance implications of hard-faults in two non-architectural resources: a line predictor and a return-address-stack. In particular, a simulation based analysis of a high-end processor that experiences a stuck-at fault in one of its most frequently used cells in the return-address-stack and the line predictor, revealed a degradation up to 9 % and 3%, respectively. When a stuck-at hard-fault occurs in one of the output drivers the slowdown can be as high as 34 % in the return-address-stack and 19 % in the line predictor