Analysis of the Feasible Dynamic Reconfiguration Criteria for FPGA Structure in Sharing Fashion

Abstract. The dynamically reconfigurable hardware can be changed during run-time and more areas of an application can be mapped to the hardware in sharing fashion with potential of parallel processing. This leads to an overall improvement in performance of reconfigurable FPGA fabric as the hardware accelerator. But the concurrence in sharing FPGA architecture is becoming an important issue. In this context, we develop a simple and intuitive algorithm to explain when and why a dynamic reconfiguration solution is lead to efficient and fair allocation of FPGA resource in sharing fashion. The operation volume increase or decrease policies are examined. We formulated a set of conditions that any increase or decrease policy should satisfy to ensure convergence to efficient and fair state in a distributed manner. Using the optimization considerations in convergence to fairness we showed that additive increase with multiplicative decrease of operation volume is the optimal policy.