Evaluation of Design Error Models for Verification Testing of Microprocessors 1

We are developing a design verification methodology for microprocessor hardware based on modeling design errors and generating simulation vectors for the modeled errors via physical fault testing techniques. A class of conditional error models has recently been proposed for use with this methodology and is the subject of this paper. We analyze the classes of errors that are guaranteed to be detected by complete test sets for the conditional errors for gate level circuits. We also report experimental work-in-progress aimed at comparing the usefulness of different design error models for verification testing of microprocessors. In these experiments the coverage of test sets for both synthetic and actual errors is computed. 1