Dynamic optimization in hardware

Dynamic instruction count and instruction-level parallelism (ILP) are two limiting factors for high performance computing. Processor designers typically attack these limit-ing factors through processor frequency scaling, and by creating superscalar processors to leverage the inherent ILP in applications. This dissertation adopts a complementary ap-proach of attacking these two factors by using integrated dynamic optimization hardware to directly reduce dynamic instruction count and increase ILP. On a broad level, we describe the relationship between well-known compiler opti-mization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous optimization and discrete optimization. Continuous optimization optimizes instructions in the processor pipeline prior to execution. It is primarily useful for reducing processor resource contention and increasing ILP. Discrete optimization captures reusable chunks of the dynamic instruc-tion stream, optimizes them, and then sequences them back into execution. Its primary benefits come from reducing instruction count and increasing ILP. The benefits of these two models are mostly orthogonal, and, therefore, they can be combined to provide large